1. Field of the Invention
This invention relates to metal oxide semiconductor (MOS) structures and more particularly to MOS structures on a compound semiconductor, such as GaAs, and to methods of forming a gate insulator, such as SiO.sub.2, on a compound semiconductor.
2. Description of the Prior Art
Heretofore, attempts to realize metal-oxide-semiconductor structures on GaAs have been unsuccessful due to the very high density of interface states which are nearly always present at exposed GaAs surfaces or at interfaces with virtually all materials. The presence of the high density of interface states causes the pinning of the GaAs interface Fermi level. The pinning of the interface Fermi level is so tenacious, that it is the basis for reproducible metal-semiconductor GaAs MESFET devices The Fermi level is pinned approximately midgap, i.e. midway between the conduction band energy and the valence band energy at the surface.
It is desirable, however, in many applications to unpin the Fermi level Prior art attempts to unpin the Fermi level at the surface have involved chemical treatments of the GaAs surface. These include the formation of surface Ga oxides by treatment with water and light as described by Offsey, et al. Appl. Phys. Lett. 48, 475 (1986) and passivation by a sodium sulfide treatment, as described by Sandroff, et al., Appl. Phys. Let. 51, 33 (1987). In addition, it is known that thin overlayers of Ge or Si on GaAs can result in different barrier heights, showing modification of surface Fermi level position, as shown by Grant, et al., J. Vac. Sci. Tech B5(4) 1015 (1987). It has not been shown in any prior work, however, that the surface Fermi level position can be moved throughout the forbidden energy gap.
In the fabrication of MOS structures on GaAs, the surface Fermi level should be unpinned to allow the Fermi level to be varied by bias voltages applied to the gate electrode. The movement of the Fermi level permits the device to be operated in an inversion mode or an accumulation mode, depending on the polarity of the bias applied to the gate. In addition, a low leakage gate insulator material is necessary to maximize the gate control of charge carriers.
None of the prior art unpinning techniques have allowed the formation of a low leakage insulating material on the treated surface, without repinning the interfacial Fermi level. MOS capacitor structures with a leaky dielectric generally exhibit poor C-V characteristics, since the channel and metal layers can exchange charge. Even a GaAs surface which is unpinned will not exhibit good charge control by the gate electrode when the insulator is leaky.